Publications

You can also find my articles on my Google Scholar profile

Books

Jain, Vikram., Verhelst, Marian., Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning: Journey from Single-core Acceleration to Multi-core Heterogeneous Systems. United States: Springer Nature Switzerland, 2023.

Theses

Vikram Jain, M Verhelst, P Karsmakers, “Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning”, Ph.D. Thesis, KU Leuven, 2023

Vikram Jain, “Reconfigurable-Rate Product Decoders for Rate-Adaptable Optical Networks”, Master Thesis, Chalmers University of Technology, 2018

Journals

Vikram Jain, S. Giraldo, J. D. Roose, L. Mei, B. Boons and M. Verhelst, “TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge,” in IEEE Journal of Solid-State Circuits, vol. 58, no. 8, pp. 2360-2371, Aug. 2023, doi: 10.1109/JSSC.2023.3236566.

P. Houshmand, G.M. Sarda, Vikram Jain, et al., “DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge,” in IEEE Journal of Solid-State Circuits, vol. 58, no. 1, pp. 203-215, Jan. 2023, doi: 10.1109/JSSC.2022.3214064.

Jain, Vikram., Jadhav, N. & Verhelst, M., “Enabling real-time object detection on low cost FPGAs”. J Real-Time Image Proc 19, 217–229 (2022).

J. S. P. Giraldo, Vikram Jain and M. Verhelst, “Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 12, pp. 2220-2228, Dec. 2021, doi: 10.1109/TVLSI.2021.3120189.

L. Mei, P. Houshmand, Vikram Jain, S. Giraldo and M. Verhelst, “ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators,” in IEEE Transactions on Computers, vol. 70, no. 8, pp. 1160-1174, 1 Aug. 2021, doi: 10.1109/TC.2021.3059962.

Vikram Jain, C. Fougstedt and P. Larsson-Edefors, “Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 1, pp. 25-34, Jan. 2021, doi: 10.1109/TCSI.2020.3035419.

Mei, Linyan, Pouya Houshmand, Vikram Jain, Sebastian Giraldo, and Marian Verhelst. “ZigZag: A memory-centric rapid DNN accelerator design space exploration framework.” arXiv preprint arXiv:2007.11360 (2020).

Conferences

Vikram Jain, S. Giraldo, J. D. Roose, B. Boons, L. Mei and M. Verhelst, “TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge,” 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2022, pp. 20-21, doi: 10.1109/VLSITechnologyandCir46769.2022.9830409.

K. Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe M. Sarda, Vikram Jain et al., “DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC,” 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731716.

Vikram Jain, L. Mei and M. Verhelst, “Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks,” 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458553.

Vikram Jain, C. Fougstedt and P. Larsson-Edefors, “Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication,” 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genoa, Italy, 2019, pp. 45-48, doi: 10.1109/ICECS46596.2019.8964930.

M. D. Gomony et al., “PetaOps/W edge-AI μ\mu Processors: Myth or reality?,” 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6, doi: 10.23919/DATE56975.2023.10136926.

Gomony, Manil, F. Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui et al. “CONVOLVE: Smart and seamless design of smart edge processors.” arXiv preprint arXiv:2212.00873 (2022).

Workshops

Vikram Jain, G Sarda, P Houshmand, M Verhelst, “Towards the next generation Heterogeneous Multi-core Multi-accelerator Architectures for Machine Learning”, Spring 2022 RISC-V Week, Location: Paris, France, 2022

V Jain, S Giraldo, M Verhelst, “VERSA: A 0.8-17.1 TOPS/W, 1.68 uW-20 mW, versatile system-on-chip with state-retentive eMRAM for machine learning inference”, 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022